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Generate VHDL, SystemVerilog, html, rst, pdf from an IPXACT description

Project Description

ipxact2systemverilog ipxact2rst ipxact2vhdl

This software takes an IP-XACT description of register banks, and generates synthesizable VHDL and SystemVerilog packages and ReStructuredText documents. It ONLY considers register bank descriptions. The software does not generate OVM or UVM testbench packages. In the example/tb directory there is an example of how to use the generated packages.


pip3 install ipxact2systemverilog
ipxact2systemverilog --srcFile FILE --destDir DIR
ipxact2rst --srcFile FILE --destDir DIR
ipxact2vhdl --srcFile FILE --destDir DIR



Testing the example file


If Modelsim is installed:

make compile
make sim


You can use to make a pdf from the generated reStructuredText. You can use to convert to almost any fileformat.


To validate your xml

xmllint --noout --schema ipxact2systemverilog/xml/component.xsd  example/input/test.xml


pip3 install docutils lxml tabulate

Dependencies used by makefile

These are not needed for ipxact2systemverilog, but used for generating some of the files in example/output

pip2 install rst2pdf
brew install pandoc

Working in development mode for pypi

pip install -e .
python sdist
python sdist upload -r pypitest
python sdist upload -r pypi


  • Should compile the verilog output with but sadly icarus does not support enough SV yet
  • A better testbench for the generated packages should be implemented.
  • More complicated IPXACT files should be added and tried out.
  • Add support for the SystemVerilog generator to have a register field of an enumerated type.
  • Use to enable dumping out the modified XML
  • Support DIM
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File Name & Checksum SHA256 Checksum Help Version File Type Upload Date
ipxact2systemverilog-1.0.2.tar.gz (43.3 kB) Copy SHA256 Checksum SHA256 Source Aug 19, 2017

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